|
Program
Code : XFAFFD6
Program Name: Fundamental of FPGA
Design, Design for Performance & Advanced FPGA Implementation
ISE 7.1
Duration :
5 Days
(Cost
Per Person Rs 26,000/-) An incentive discount of 5% is given on receiving
two nominations and 10% for receiving three or
more nominations from same company.
| Training
Program Details |
|
Skills
Gained:
- Implement
an FPGA design with the Xilinx Project Navigator.
- Use
Architecture Wizard to create DCM instantiations.
- Use
the PACE tool to assign pin locations.
- Read
reports to determine whether design goals were
met.
- Assign
pin locations and enter basic global timing constraints
using the Constraints Editor.
- Locate
and modify the implementation options.
- Make
path-specific timing constraints using the Xilinx
Constraints Editor
- Improve
design performance and manage software runtime
by using MPPR and re-entrant routing
- Create
customized cores using the CORE GeneratorT System
- Run
a behavioral simulation on an FPGA design that
includes cores
- Improve
design performance by duplicating flip-flops and
pipelining
- Analyze
design performance via timing reports and determine
the steps necessary to achieve timing closure.
- Take
advantage of Xilinx tools' scripting capabilities.
- Create
and edit constraints for hand placing logic and
creating timing constraints.
- Create
RPMs for improved performance of critical paths.
- Decrease
run-time through the use of Incremental Design
Techniques.
- Use
the Floorplanner to create effective layouts of
your design and decrease Place and Route run-times.
- Take
advantage of the Virtex-II architecture through
increased knowledge of I/O layout, high-speed I/O,
and clock design.
- Make
changes to a post-place and route design in the
FPGA Editor.
|
LEVEL: Fundamental
to Advanced
Goal: Learn how to use ISE Series software quickly and reduce
design time.
Course Description: This comprehensive course
provides students with an introduction to designing
with Xilinx FPGAs using the ISE Series software tools.
This course covers ISE 5 features such as Architecture
Wizard and the Pin and Area Constraint Editor (PACE).
Other topics include design planning, implementation
options, and global timing constraints.
Who should attend? Digital designers with basic
knowledge of an HDL but new to Xilinx FPGAs or / and
FPGA designers with basic knowledge of an HDL and some
experience with the Xilinx ISE software tools, engineers
seeking advanced training in using Xilinx tools to
improve FPGA performance and utilization, while also
increasing productivity.
PREREQUISITES:
Working knowledge of HDL (VHDL or Verilog) , New
to Xilinx FPGAs
|
| Training
Outline - Fundamentals
of FPGA design |
- Introduction
- Advanced
Control Through Scriptingxx
Command Line Implementation
UCF Editing
Lab 1: UCF and Scripting
Creating your Own RPM
Lab 2: RPM
- Reduce
Debug Time
FPGA Editor: Viewing and Editing a Routed Design
Lab 3: FPGA Editor
- Improve
Your Timing - Handcrafting Performance
Incremental Design Techniques
Floorplanner: Effective Layout
Lab 4: Incremental Design
- Optimize
Your Design for Xilinx Architecture
High Speed I/O
Advanced Virtex-II Architecture and Design
Lab 5: Clock Design
|
| Training
Outline - Advanced
FPGA Implementation |
- Review
from Fundamentals Course
- Advanced
VirtexT-II Architecture
- FPGA
Design Techniques
- CORE
Generator System
- Lab
1: CORE Generator System
- Designing
with the Digital Clock Manager
- Lab
2: Digital Clock Manager
- Achieving
Timing Closure
- Timing
Groups and OFFSET Constraints
- Path-Specific
Timing Constraints
- Lab
3: Achieving Timing Closure
- Advanced
Implementation Options
- Advanced
Control Through Scripting
- Command
Line Implementation
- UCF
Editing
- Lab
4: UCF and Scripting
- Creating
your Own RPM
- Lab
5: RPM
- Reduce
Debug Time
- FPGA
Editor: Viewing and Editing a Routed Design
- Lab
6: FPGA Editor
- Improve
Your Timing - Handcrafting Performance
- Incremental
Design Techniques
- Floorplanner:
Effective Layout
- Lab
7: Incremental Design
|
| LAB
DESCRIPTIONS |
- Lab
1 - CORE Generator System: Create a core,
instantiate the core into VHDL or Verilog source
code, and run behavioral simulation.
- Lab
2 - Xilinx Review of Global Timing Constraints:
This lab is a quick review of using the Constraints
Editor, and introduces the lab design that is
used throughout the course. Gets you into the
software quickly.
- Lab
3 - Achieving Timing Closure: Review timing
reports and enter path-specific timing constraints
to meet performance goals.
- Lab
4 - UCF and Scripting: Write constraints
directly into a UCF file. Write program commands
into a batch file to implement the design. Finally,
modify the constraint values and program switches
to obtain the greatest possible performance from
the design.
- Lab
5 - RPM: Create an RPM in a UCF file. Use
the Timing Analyzer to find a path that is not
meeting timing constraints and identify the components
of that path. Finally, RLOC the components to
create the RPM and improve timing for that path.
- Lab
6 - FPGA Editor: Use the FPGA Editor to view
and edit the correlate and accumulate design.
Analyze the contents of a CLB; add a probe; remove,
place, and modify components, and analyze long
nets.
- Lab
7 - Incremental Design: Use incremental design
techniques to gain faster turnaround times when
you make changes to a module.
|
Click
here to View the list of all corporate programmes
|
corporate
training program