: : Sandeepani - School of VLSI Design

Program Code : XFAFD5
Program Name: Xilinx Advanced FPGA Implementation - ISE 7.1
Duration : 2 Days
(Cost Per Person Rs 12,000/-. )

Training Program Details
Skills Gained: Make path-specific timing constraints using the Xilinx Constraints Editor Improve design performance and manage software runtime by using MPPR and re-entrant routing Create customized cores using the CORE GeneratorT System Run a behavioral simulation on an FPGA design that includes cores Improve design performance by duplicating flip-flops and pipelining Analyze design performance via timing reports and determine the steps necessary to achieve timing closure. Take advantage of Xilinx tools' scripting capabilities. Create and edit constraints for hand placing logic and creating timing constraints. Create RPMs for improved performance of critical paths. Decrease run-time through the use of Incremental Design Techniques. Use the Floorplanner to create effective layouts of your design and decrease Place and Route run-times. Take advantage of the Virtex-II architecture through increased knowledge of I/O layout, high-speed I/O, and clock design. Make changes to a post-place and route design in the FPGA Editor.	LEVEL: Intermediate to Advanced Goal: Learn how to use ISE Series software quickly and reduce design time. Course Description: Learn design techniques to help improve your design's performance & advanced use of Xilinx tools. This course builds on the principles covered in our Fundamentals of FPGA Design course with an emphasis on achieving timing closure. Topics include: FPGA design techniques, the CORE Generator System, timing analysis, advanced timing constraints, and advanced implementation options, scripting, floorplanning, proper coding, use of VirtexT-II high speed I/O, using FPGA Editor, I/O location constraints, creating RPMs (Relationally Placed Macros), and detailed coverage of the newest Xilinx FPGAs. Who should attend? FPGA designers with basic knowledge of an HDL and some experience with the Xilinx ISE software tools, engineers seeking advanced training in using Xilinx tools to improve FPGA performance and utilization, while also increasing productivity. PREREQUISITES: Basic HDL knowledge (VHDL or Verilog) Fundamentals course or equivalent knowledge of VirtexT-II architecture, software tool flow and global timing constraints
Training Outline
Review from Fundamentals Course Advanced VirtexT-II Architecture FPGA Design Techniques CORE Generator System Lab 1: CORE Generator System Designing with the Digital Clock Manager Lab 2: Digital Clock Manager Achieving Timing Closure Timing Groups and OFFSET Constraints Path-Specific Timing Constraints Lab 3: Achieving Timing Closure Advanced Implementation Options Advanced Control Through Scripting Command Line Implementation UCF Editing Lab 4: UCF and Scripting Creating your Own RPM Lab 5: RPM Reduce Debug Time FPGA Editor: Viewing and Editing a Routed Design Lab 6: FPGA Editor Improve Your Timing - Handcrafting Performance Incremental Design Techniques Floorplanner: Effective Layout Lab 7: Incremental Design
LAB DESCRIPTIONS
Lab 1 - CORE Generator System: Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation. Lab 2 - Xilinx Review of Global Timing Constraints: This lab is a quick review of using the Constraints Editor, and introduces the lab design that is used throughout the course. Gets you into the software quickly. Lab 3 - Achieving Timing Closure: Review timing reports and enter path-specific timing constraints to meet performance goals. Lab 4 - UCF and Scripting: Write constraints directly into a UCF file. Write program commands into a batch file to implement the design. Finally, modify the constraint values and program switches to obtain the greatest possible performance from the design. Lab 5 - RPM: Create an RPM in a UCF file. Use the Timing Analyzer to find a path that is not meeting timing constraints and identify the components of that path. Finally, RLOC the components to create the RPM and improve timing for that path. Lab 6 - FPGA Editor: Use the FPGA Editor to view and edit the correlate and accumulate design. Analyze the contents of a CLB; add a probe; remove, place, and modify components, and analyze long nets. Lab 7 - Incremental Design: Use incremental design techniques to gain faster turnaround times when you make changes to a module.

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