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Program Name: DSP Implementation Techniques for Xilinx FPGAs  
  Program Code: XDIT12
  Duration: 3 Days
  Cost/Participant: Rs 27,000/-
  Level: Advanced
 
DSP IMPLEMENTATION TECHNIQUES FOR XILINX FPGAS
Course Description

This course shows you how to take advantage of the features available in the Xilinx FPGA architecture, including the Virtex™-4 FPGA, and describes how DSP algorithms can be implemented efficiently. The techniques also demonstrate which decisions at the system level have the greatest impact on the implementation process and product costs.
 
 
Who should attend?

Engineers and designers who have an interest in developing products that use digital signal processing
 
 
Prerequisites:
A fundamental understanding of digital signal processing theory, including an understanding of the following principles:
  • Sample rates
  • Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters
  • Oscillators and mixers
  • Fast Fourier Transform (FFT) algorithm
 
 
Skills Gained:
  • Describe how DSP algorithms can be implemented efficiently by using Xilinx FPGA technology
  • Identify the capabilities and features of the various Xilinx FPGA families to implement efficient DSP algorithms
  • Establish methods for the accurate estimation of silicon area consumption and cost
  • Evaluate which algorithms are best suited for FPGA implementation and identify which algorithms are less desirable
  • Assess how system-level decisions impact hardware implementation and how hardware implementation can enhance results at the system level
 
 
Software Tools:
  • Xilinx ISE 8.1i
  • Synplicity Synplify
  • Mentor Precision
  • Xilinx XST
 
 
Training Outline:

Day 1:

  • On the Same Wavelength
    • Basic Tterminology and Aacronyms used in DSP Ddesign
    • Sample rates and bit widths used in DSP Aapplications
    • DSP building blocks and processing requirements
  • Some Bits About Numbers
    • Numbering formats, range, and precision
    • Mathematical Ooperations using a variety of formats
  • Tuning the Receiver
    • Structure and Resources of Xilinx Devices
    • Estimating DSP building block sizes
Day 2:
  • Tuning the Receiver (continued)
    • Implementing the multiplication function
    • Bit-width impact on system-level decisions
  • Xilinx CORE Generator Functions and Capabilities
    • Memories are Made of This
      • Block versus distributed memory
      • SRL16E and the delay function
      • Memory aspect ratios and their manipulation
  • Selective Filters
    • FIR filter specifications and implementations
    • Selectingion of a technique for a given specification
    • Effects of halfband andIinterpolated filters
    • Creating an SDA FIR Filter with Xilinx CORE Generato
Day 3:
  • One Filter Does Not Make a System
    • Options to be considered with multiple channels
    • Interpolation and decimation
    • Rate changing and How It effects on FIR filter choice
    • Filtering algorithms that exploit device architecture
    • Importance of connectivity versus isolated functions
  • Don Not Block the Datapath
    • Numeric Ccontrolled Ooscillators and Mmixers
  • Using the FPGA as an Efficient Co-processor
    • Strategies for FFT Iimplementation
    • Achieving Bbandwidth Rrequirements of the FFT
    • Using the FPGA as an efficient co-processor
 
 
Course Exercises:

  • Sample Rates and Bit Widths
    • MAC Rates and Memory Requirements
    • Constructing a 128-Tap FIR Filter
    • Fractional Number Formats
    • Twos Complement Arithmetic
    • Summation by Addition Tree
    • Summation by Addition Chain
    • Full Adder – : How Many Slices?
    • Summation Structure Sizes
    • Serial Summation Structure Processing
    • An 8-Bit by 12-Bit Multiplier
    • KCM Multipliers
    • Distributed RAM for FIFO
    • Size Estimates for Delay Structures
    • Using the SRL16E as a FIFO
    • Creating Larger RAM Structures
    • Selecting a MAC FIR Technique
    • Parallel FIR Filter Size
  • SDA Filter Implementation
    • Symmetry, Interpolation, and Phases
    • Decimation Filter
    • “fs/4” Mixing and Decimation
  • Running (Moving) Average Filter
    • Designing a Numeric Controlled Oscillator (NCO)
    • The FFT: Benchmarks and Transform Time
    • Data Block Collection Time = and FFT Processing Time
    • 128-Point FFT in 1.28 m s



 

 
 
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Course Schedule :
 
# Start-Date Location Cost Per Participant Duration Regn Status Register
1 June - 14 , 2006 Hyderabad Rs 27,000/- 3 Days CLOSED
 
 
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