Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
Fundamentals of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
Lab 1: CORE Generator Software System – Create a core, instantiate the core into VHDL or Verilog source code, and run behavioral simulation.
Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.
Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.
Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.
Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.
Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.
Lab 8: ChipScope Pro Analyzer – Add an internal logic analyzer to a design to perform real-time debugging.
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