Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE™ 9.1i tool suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover Synplicity’s Synplify and the Xilinx XST tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months’ design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software 9.1i tools and the Virtex™-4 FPGAs.
Note: Labs will be based on Xilinx ISE 9.1i software.
Lab 1: Achieving Timing Closure – Create global timing constraints, read timing reports, apply path-specific constraints (multicycle and false paths), and apply advanced implementation options.
Lab 2: Tcl Scripting – Write program commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.
Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 4: Advanced I/O Timing – Compose timing constraints for I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.
Lab 5: SmartCompile – Utilize SmartGuide and Partitions to preserve timing results from one iteration to the next.
Lab 6: Floorplanning – Implement a design using floorlplanned constraints to enhance the timing results over a design without floorplanning.
Lab 7: FPGA Editor – Use the FPGA Editor to view and edit a design. Analyze the contents of a CLB; add a probe; remove, place, and modify components; and analyze long nets.
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