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| Professional Development Course on VLSI Design |
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Sandeepani is a training division of CoreEL Technologies (I) Pvt. Ltd offering high-end training in VLSI Technology, with more than 9 years of Design Experience and Corporate Training.
Professional Development Course in VLSI Design is offered by CoreEL. This Advanced VLSI Training grooms fresh engineering graduates (BE/BS/MS/ME/Mtechs.) with industry exposure and knowledge. We have trained more than 6000 corporate professionals from corporate majors like Wipro, HCL, Agilent, IBM, Intel, Philips Semiconductors, GE Wipro Medical Systems, Virage Logic, GE-Satyam, ITI, BHEL, ECIL, CAIR, Tata Elxsi, National Semiconductors, Motorola … to name a few.
VLSI Professionals after completion of course from our Training School can start working on the projects and are productive from the day one in the company they join.
Professional Development Course offered by "Sandeepani - School of VLSI Design" is quite unique in the country :
- Being only authorized sole representative of Xilinx in India, Engineers undergoing training at sandeepani get access to all the possible tools to gain the best possible hands on experience on complete VLSI Technology.
- All well experienced Sr. Design and Application Engineers of CoreEL form the core faculty team of the training division. Who else can take you better through the solution for real life VLSI Design world's challenges and project management skills. We also give importance to personality development programs/sessions during the course.
- Emphasis on practical gives the confidence required to tackle the design problems. We provide 24 hrs and 7 days a week Lab Facility.
- CoreEL certification gives industry recognition to this course. This enhance career Opportunities for VLSI Professionals World wide.
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Review of digital systems
- Summary of digital basics
- Structuring and organizing digital design
- Development cycle through an example
System, board design overview
- System composition and hierarchy
- System connectivity standards
- Generic engineering modeling overview and example tools
- System design stages
- Schematic to PCB flow and tools overview
- Common board design considerations
- Component classes
- Component selection and Interpretation of datasheets
- Design and schematic work – Case Study
- Basics of system levels timing, board level simulation and wave forms for timing
FPGA architecture and FPGA as a system component
- Programmable logic evolution
- FPGA vs. CPLD
- FPGA essential building blocks
- logic mapping to the FPGA
- FPGA editor
- FPGA configuration
- Different classes of pins of an FPGA and system connectivity considerations
- Understanding packages and thermal data
- FPGA - Memory, Processor, DSP/Multiplier, Gigabit I/Os, Clock management components
- FPGA suppliers and differentiation
Getting started to Design - Schematic based FPGA design
- Concept of libraries, sources of reference
- A design problem to solve on paper by putting together the FPGA building blocks
- ISE environment
Logic design using Verilog
- Language concepts
- Design abstractions
- Hierarchy
- RTL overview
- Test bench
- Simulation vs. synthesis, basic synthesis options
- Combinatorial logic
- Sequential logic
- Finite State Machines (FSM)
- Usage of cores, Xilinx core gen and libraries
- Development stages
- Configuration management version control
- Coding guidelines
- Resource aware coding
- Verification planning
- Using scripts for simulation
FPGA implementation
- Design flow overview
- Design implementation
- Reading Reports
- Basic constraints - Timing and area
- Basics of timing analysis
- FPGA pin assignment
Advanced FPGA design
- Designing with DCM, clock management
- On-chip memory and FIFO
- Advanced timing constraints
- Timing closure strategy
- Advanced synthesis, implementations options
- Power estimation methods and its importance
Embedded debugging
- Introduction to logic state capturing
- Triggers, data capture
- Different options to capture
- On board debugging strategy
Introduction to Embedded system design on FPGA
- An overview of XILINX solution for Embedded System Design on FPGA - Tools support and Design Flow
- Configuration of Hardware and Software platform for Embedded System Design
Introduction to DSP designs on FPGA
- An overview of XILINX solution for DSP design – Tools support and Design Flow
- Design and Verification of DSP application on FPGA
Multi Gigabit Transceivers (MGT)
- Introduction to serial IO, line encoding, clock correction
- Application of MGT
Project Orientation & Project Management overview
Industry Standard Project
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- 10 weeks including 2 weeks of industry standard project.
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- Eligibility:
BE / ME in EE, E&C, CSE, IT, Telecom, Instrumentation or MSc Electronics.
- Selection Process:
- Online Test
- 25 objective type questions. For on line test you have to first register
with us.
- Candidates short listed based on their Academics and Performance in On-Line test will
be called for Written test and Final Round of Interview (Technical) in Bangalore.
- Subjects to be referred:
- Basics of Digital and Analog Electronics.
- Microprocessor Fundamentals.
- General Aptitude.
- Basics of Programming
- Faculty:
- Technical Managers
- Project Leaders
- Sr. Design Engineers
- Application Engineering Managers
- Sr. Application Engineers
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Course Timings
- Official Lectures, Presentations and Labs will be conducted everyday from 10:30 AM to 4:30 PM, five days a week.
- Labs facilities will be provided 24 hours and all 7 days a week for extra practice and completion of assignments.
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Course Fee
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| Course Fee- Installment (INR 49, 500/- + Tax) |
| Registration Fee |
9,066/- |
| I Installment |
27,199/- |
| II Installment |
13,236/- |
| Service Tax(10.3 %) |
5,099/- |
| Total Fee (Inclusive of Tax) |
54,599/- |
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| Lump sum Course Fee (INR 47,000/- + Tax) |
| Registration Fee |
9,066/- |
| First & Final Installment |
37,934/- |
| Service Tax(10.3 %) |
4,841/- |
| Total Fee (Inclusive of Tax) |
51,841/- |
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| Reference Books |
- We recommend the following books for purchase which will be helpful to you at the time of our Professional Development Course
- VHDL - Douglas Perry
- Verilog HDL - Samir Palnitkar (Indian Edition)
- Logic and Computer Design Fundamentals 2nd Edition - M. Morris Mano and Charles R. Kime
- FPGA-Based System Design – Wayne Wolf.
We will be providing our own material and lab books for your daily assignments & practices.
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Professional Development Course Calendar
| # |
Code |
Start-Date |
Location |
Cost Per Participant |
Duration |
Regn.Status |
Registration |
| 1 |
pgdip |
September
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11
,
2008
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Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 2 |
pgdip |
December
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4
,
2008
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 3 |
pgdip |
March
-
6
,
2009
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 4 |
pgdip |
June
-
12
,
2009
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 5 |
pgdip |
August
-
18
,
2009
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 6 |
pgdip |
November
-
10
,
2009
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 7 |
pgdip |
February
-
1
,
2010
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 8 |
pgdip |
April
-
28
,
2010
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 9 |
pgdip |
July
-
15
,
2010
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 10 |
pgdip |
July
-
30
,
2010
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
CLOSED |
|
| 11 |
pgdip |
October
-
15
,
2010
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
OPEN |
Register
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| 12 |
pgdip |
January
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10
,
2011
|
Bangalore |
Rs 49,500/- + (service tax) |
10 Weeks |
OPEN |
Register
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