• Arithmetic Circuits 
• Basic data processing circuits
• Latches and Flip Flops
• Shift registers and counters
• State Machines
• Design examples and case studies

• Introduction 
• Design Units
• Language Constructs
• Design Styles
• Concurrent and Sequential Elements
• State Machines 
• Memories
• Functions and Procedures
• File I/O Operations
• Test Bench Design and Coding
• Case Studies - FIR Filter / Telecom Transmitter
  
  

• Language Constructs
• Modelling Combinatorial and Sequential Circuits
• Design & Modeling recommendations 
• Verification
• Design Examples 
  

• Programmable Logic Devices
• CPLD Families like CR-II
• Virtex-II and Virtex-II Pro Architecture
• Xilinx Design Flow
• Timing Constraints
• Implementation Details
• Synchronous Design Techniques
• Advanced FPGA Design tips.
• Device Programming
  
  

• Introduction to VLSI Design Methodologies
• Review of MOS Transistor Theory
• Static CMOS Logic Circuits
• CMOS Inverter
• Basic Combinational Logic Circuits
• Pass Transistor Logic Circuits 
• Transmission Gates
• Dynamic CMOS Logic Circuits
• Physical Design 
  
  • Theory and Layout Using IC Station (Mentor Graphics Tools)
  • IC Layout Using Blast Fusion. (Magma Tools)
• Physical Verification
  • Using Calibre DRC (Mentor Graphics Tools)
  • Using Calibre LVS
  • Using Calibre PEX
• Circuit Simulation
  • Using ELDO (Mentor Graphics Tools)

• Basics of CMOS Analog Design
• Simulation with SPICE
• Mixed Signal Design Methodology and the Design Flow
• Behavioural Modelling Concepts
• Mixed Signal Simulation
• Transistor Models and Process Files
• Case Studies - VCO: Analysis and Design
• PLL: Multi Abstraction Simulation
• EDA Tools Used: Design Architect IC, ELDO and Advance MS 
  
  

MENTOR GRAPHICS

• Front End Tools - HDL Designer Series, Modelsim, Leonardo Spectrum. 
• SST Velocity - Static Timing Analysis.
• Digital ASIC Back End Tool - IC Station, Calibre and x Calibre.
• Analog Design Simulation - ELDO.
• DFT Tools - Fast Scan, MBIST and DFT Advisor.

• Sun Solaris Platform
• Windows NT Platform

• Design Specifications
• RTL Design & Documentation
• Test bench design and documentation
• Coding and Verification, Synthesis Report, P & R Report. 

• PCI Bus Arbiter Core.
• Loss of Multi Frame Detector in SONET/SDH Frames.
• ATM Cell Delineation Core.
• Hardware Implementation of an N Tap FIR Filter. 
• FPGA based implementation of E1 Framer.
• 32 bit 64 MHz PCI Interface with Gigabit Ethernet MAC
• Implementation of E1 to E2 Mux.
• Implementation of DFT on DES and 3-DES IP Cores
• Design & Implementation of Interpolated Filter (DSP domain)
• Architectural Study and Implementation of 12 Bit SAR ADC.
• Full Custom/ Semi Custom Implementation of 8 Bit ALU.
• Full Custom ASIC Implementation of Adders.
• Asynchronous Multi Channel FIFO
• Implementation of SCAN and ATPG on 8031 Core
• PLB Bridge Implementation for IBM Power PC 405D
• Bit Serial Implementation FIR Filter Semi Custom Approach using TSMC
• Bus Interface Unit of 8086 Microprocessor
• DES/3DES Integration with 8051 and verification
• Memory Management Unit of ARM 1020E Processor
• RTL Implementation of 1024 point FFT Core (Radix 4) and Cross Verification using Matlab.
  
  And Many Many More.