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 Program Code : MDFT1
 Program Name: Design for Test
 Duration          : 3 Days
 

 

Training Program Details
Contents
DFT Advisor ½ day

  • DFT Advisor Overview

  • Scan Methodology

    1. Scan Cells
    2. Full Scan
    3. Partial Scan
    4. Hierarchical Scan.

  • Test Logic and Test Point Insertion

  • DFT Insight and its Use in DRC Debugging

  • Multiple Clocks

    1. Minimize clock skew
    2. Merge Different Clocks and clock edges
    3. Using lockup latches

  • Balancing Scan Chains

  • Scan Chain Stitching

    1. Scan Chain Ordering & Stitching
    2. Unstitched scan cells and
    3. Stitching existing scan cells.
FastScan 1 ½ days 

  • Fastscan Overview and tool flow overview

  • Fastscan setup and ATPG setup files

  1. Dofile

  2. Enhanced Procedure File

  • DRCs and ATPG configuration

  • Generating and Saving Test Patterns (Command "create patterns -compact")

  • ATPG Reporting and Test Coverage Reporting

  • Fault Collapsing and Adding no faults

  • External fault list and Fault Sampling

  • Fastscan test pattern types

  1. Basic Patterns

  2. Clock PO

  3. Clock Sequential

  4. Ram Sequential

  5. Multi Load Patterns

  • AT Speed ATPG - Transition & Path Delay Fault model and testing

  • Creating Transition Fault Patterns

  1. Launch Off Shift

  2. Broadside

  • Creating Path delay Fault Patterns (Path definition files)

  • IDDQ testing and creating IDDQ patterns

  • Compression Techniques

  1. Static Compression

  2. Dynamic Compression

  3. Multi Clock Compression

  • Fault Hierarchy - Fault grading patterns across Fault Models

  • Black Boxes and Testing Embedded Blocks

  • Testing Embedded Memories

  1. Macrotest and Synchronous Macrotest

  2. Memory BIST, BIST bypass and initialization issues

  • Diagnostics

  • Simulation Mismatches

Memory BIST ½ day
  • Types of Memory Testing
  • Advantages and Disadvantages of Memory BIST 
  • Memory Fault Types
    1. Stuck at
    2. Transition
    3. Coupling
    4. Neighborhood Pattern Sensitive 
  • Memory Test Algorithms
  • Memory BIST architecture and its operation
  • Implementing variations in Memory BIST
    1. Algorithms
    2. Data Backgrounds
    3. Comparator
    4. Compressor  
  • Configuring the Memory BIST Circuitry and verifying the BIST circuitry
  • BIST for Multi Port Memories and Multiple Memories
    1. Sequential testing
    2. Concurrent testing
  • Diagnostics - individual or separate fail flags
  • Full speed testing of Memories
Boundary Scan BSD Architect ½ day

  • BSD Architect Inputs and outputs

  • Basic BSDArchitect Process Flow

  • Creating Default Circuitry and performing basic customizations

  • Configuring the boundary scan chain

  • Inserting Technology specific Boundary Scan circuitry

  • BS Architecture with Internal Scan

  • Compiling and Verifying the Boundary Scan circuitry


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Course schedule

#  Code Start-Date Location Cost Per Participant Duration Registration Status Registration
1 MDFT1 February - 9 , 2005 Bangalore .. 3 Days CLOSED  

 
 
 
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