: : Sandeepani - School of VLSI Design

Program Code : DFT8
Program Name: Design for Test Methodology (DFT)
Duration : 3 Days

Training Program Details
Course overview : This course is aimed at ASIC design engineers, test engineers, CAD engineers and engineering managers. Not only will you learn about the DFT concepts and methodologies, but also efficient means of employing the software tools to implement DFT on your design. A prerequisite to this training programme is knowledge of digital logic design and a basic familiarity with Solaris operating system. Today, the Semiconductor Industry is evolving on many fronts. Smaller geometries on silicon Reduction of internal voltage levels The integration of huge amount of memory and the integration of large amounts of logic on system on chip devices. The use of IP cores, complex megacells and macrocells These industry changes make quality and reliability requirements more important than ever, but at the same time are creating aggressive challenges for high quality test and economics of test. Attending a DFT Training Program is an investment that will pay for itself with the first DFT design that you begin. The Mentor Graphics certified program, conducted by our DFT trainers is well structured and fast-paced, covering all aspects of DFT in the scheduled time. Hands-on experience using Mentor Graphics DFT tools throughout the sessions ensure that the information is well grasped and applied to practical applications. The person attending the program can become an in-house expert whose expertise can be a good value addition to your ASIC design team.
Contents
Scan and ATPG
Module Structured DFT Methodology	Focus Scan Design Scan Architectures DFT Design Library Test Strategy- Full versus Partial Scan Fault Models Fault Simulation and Fault Classification Test Metrics
Module Scan Insertion using DFTAdvisor	Focus User Interface Overview Setting up Scan Information Design Rule Checking basics Design Flattening and Learning Test Logic Insertion Test Points
Module Combinatorial ATPG using FastScan and Sequential ATPG using Flextest	Focus Setting up the tool for ATPG User Interface Overview Test Procedure File basics Design Rules Checking basics Design Flattening and Learning Test data generation Fault Analysis Fault Simulation Pattern Compression Pattern Ordering Test Vector Formatting ATPG on a Boundary Scan Design
Module Graphical Debugging using DFTInsight	Focus Debugging DRC violations Analyzing the netlist
Boundary Scan Design
Module IEEE 1149.1 Boundary Scan Architecture	Focus TAP Controller Boundary Scan Registers Instruction Register Boundary Scan Instructions Customized Boundary Scan BSDL files
Module Boundary Scan Insertion using Mentor's BSDArchitect	Focus BSDArchitect flow Setting up boundary scan specification Boundary Scan Synthesis Boundary Scan Customizations Verifying Boundary Scan Circuitry
Memory BIST
Module Memory BIST	Focus Understanding BIST Memory BIST Architecture Memory testing and Fault types
Module BIST Insertion using Mentor's MBISTArchitect	Focus MBISTArchitect flow Inserting Memory BIST structures Memory BIST Variations Verifying Memory BIST Logic Synthesizing the design Verifying the Gate Level Design

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