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The
program on Calibre, the industry standard for Deep
Submicron Physical Verification will focus on the
usage of Mentor Graphics Calibre software in your
layout verification flow and will empower you to
analyze the Calibre DRC and LVS results successfully
in coordination with a layout editor.
Training experts from the EDA industry will conduct the training
program certified by Mentor Graphics Corporation, US.
The program is well structured and fast-paced, covering all aspects
of Calibre usage. Besides examining each and every aspect of Calibre
usage, the program also encompasses the following in the lectures:
- IC
Layout Verification Overview
- Introduction
to the Calibre toolset
- DRC
concepts and basic DRC checks
- Complex
DRC checks
- DRC
examples and Debugging
- Hierarchical
DRC
- Overview
of Flat and Hierarchical LVS
- LVS
Shorts and Opens
- Power
Ground Short Isolation
- Device
Recognition and Connectivity Extraction
- LVS
Texting
Our
Industry-Expert instructors will ensure that each
and every step in the design process covered in the
lectures is reinforced through practical sessions
coupled with hands-on tool usage using today's industry
standard solutions.
In
addition to the formal presentations we believe
that the program will provide an exceptional opportunity
for design engineers to exchange ideas, discuss
problems and explore solutions |
Who
Should Attend?
- IC
Layout Engineers and Layout Verification specialists
who will use Calibre DRC and LVS tools for layout
verification.
- Front-end
Design engineers who would like to have a better
understanding of the back-end verification flow.
Prerequisites
- Knowledge
of IC Layout techniques and procedures
- Experience
with an IC layout editing tool
- Familiarity
with UNIX
- Knowledge
of layout verification concepts and tools (helpful
but not required).
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Learn
how to
- Use
Calibre DRC and LVS in the flat and hierarchical
modes
- Debug
the flat and hierarchical DRC and LVS results
using Calibre RVE (Results Viewing Environment)
and a layout editor
- Interpret
the various specification statements in your
rulefile dealing with layout and source input,
DRC and LVS results databases and reports,
layer definitions, derived layers, DRC rulechecks,
LVS device recognition statements, CONNECT
statements
- Interpret
simple DRC checks such as width, spacing, enclosure
checks
- Interpret
complex DRC checks such as antenna checks,
current flow checks
- Identify
and locate the following DRC-related problems:
external spacing of edges on different or same
layers; internal spacing of edges on different
or same layers; measurement of geometry on
one layer enclosed by geometry on another
- Identify
and locate the following LVS-related problems:
shorts and opens, including those on power
and/or ground nets; floating or isolated nets;
pin swapping; device problems; soft-connections;
and texting (naming) problems
- Interface
Calibre to tools from other vendors
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corporate
training program