: : Sandeepani - School of VLSI Design

Corporate training program

Program Code :

EHSM16

Program Name :

Effective HDL simulation using ModelSim

Duration :

3 Days

(Day 1 > Day 2 > Day 3)

Course overview :

The program is aimed at both front-end design engineers and verification/test engineers along with FPGA Designers, ASIC Designers, ModelSim Users, Verification Engineers, Hardware, Software and System Engineers who perform VHDL, Verilog or mixed-VHDL/Verilog simulation and analysis.

Focus :

Modelsim tool structure and verification flow
Architecture of Modelsim
Design and Verification Language Support
Other standards support in Modelsim
Design flow with Modelsim

Contents

Day 1

MODULE 1

Understanding the GUI features

FOCUS :

Introduction to projects
Getting started with projects
Changing compilation order
Modelsim GUI windows
Specifying project settings and compilation properties

MODULE 2

Managing libraries for simulation

FOCUS :

Design library and resource library overview
Working with design libraries
Specifying resource libraries
Importing FPGA libraries
Source code protection

MODULE 3

SystemC,VHDL and Verilog Simulations

FOCUS :

Flow for SystemC, VHDL and Verilog simulation
Using Pre-compiled libraries for simulation
Simulation with an elaboration file
GUI, Command line and Batch mode simulations
Mixed language simulations

MODULE 4

Compiling for High Performance

FOCUS :

Usage of different compiler optimization switches
Improving performance on RTL and Gatelevel designs
Referencing the optimized design
Enabling design object visibility
Event order and Optimized designs

MODULE 5

Verification language Support in Modelsim

FOCUS :PSL

Introduction to PSL Assertions
- Definition
- Types of Assertions
- PSL Assertion language
Using Assertions in Modelsim

Assertion flow
Limitations

Compiling and Simulating Assertions
Managing Assertions
Viewing and Reporting Assertions

Day 2

MODULE 6

Waveform comparison and Code coverage

FOCUS :PSL

Waveform comparison

Modes of comparison
Comparing hierarchial and flattened designs
Graphic interface to waveform compare
Waveform compare commands
Compare objects in list window

Code coverage

Introduction
Coverage metrics supported in Modelsim
Enabling Code coverage
Viewing coverage data in source window
Filtering coverage data
Saving and re-loading coverage data
Coverage statistics details
Merging coverage results
Understanding the GUI features

MODULE 7

Performance and Memory Profiler

FOCUS :

Introduction to performance and Memory analysis
Inerpreting performance and Memory analysis
Performance and Memory commands

MODULE 8

Standard Delay Format Timing Annotation

FOCUS :

Specifying SDF files for simulation
Instance specification
SDF specification with GUI Errors and Warnings
SDF for mixed VHDL and Verilog designs
Interconnect delays
Disabling Timing checks

MODULE 9

Checkpoint and Restore

FOCUS :

Checkpoint and restoring simulations
Checkpoint File contents
Difference between checkpoint restore and restart
Controlling checkpoint file compression

Day 3

MODULE 10

Signal Spy

FOCUS :

Introduction
Using the Modelsim signal spy tasks
- signal force
- signal spy
- signal release

MODULE 11

Functional coverage with PSL and Modelsim

FOCUS :

Introduction
Compiling and simulating functional coverage directives
Viewing coverage statistics
Reloading/merging functional coverage data
Creating reactive testbench with endpoint directives

MODULE 12

SystemC Simulation

FOCUS :

Introduction
Usage flow for SystemC only designs
Linking the compiled source
Debugging the design
SystemC object and display type in Modelsim
Troubleshooting SystemC errors

MODULE 13

System Verilog

FOCUS :

Introduction
System Verilog Design constructs
System verilog verification constructs
System verilog Assertions

MODULE 14

Best practices

FOCUS :

Tips and Techniques to improve the simulation speed
Tips and Techniques for debugging designs

Click here to View the list of all corporate programmes

For more details contact us or make online enquiry.

Course schedule
#	Code	Start-Date	Location	Cost Per Participant	Duration	Registration Status	Registration
1	EHSM16	February - 2 , 2005	Bangalore	..	3 Days	CLOSED
2	EHSM16	June - 28 , 2005	Bangalore	..	3 Days	CLOSED
3	EHSM16	March - 28 , 2007	Bangalore	..	3 Days	CLOSED

	Privacy \| Legal
Website design by www.xtde.net	Copyright © Sandeepani 2005