| # |
Course
Module |
Tools
used |
Period |
| 1 |
High
Level Design Methodology
(Verilog IEEE 1395) |
ModelSim
for Simulation
Leonardo for Synthesis
Xilinx Foundation Series
Platform: Windows NT |
2
Weeks - Full Time
4 Weeks - Part time |
| 2 |
High
Level Design Methodology
(VHDL IEEE 1076) |
ModelSim
for Simulation
Leonardo for Synthesis
Xilinx Foundation Series
Platform: Windows NT |
2
Weeks - Full Time |
| 3 |
FPGA
Design Methodology |
ModelSim
for Simulation
Leonardo for Synthesis
Xilinx Foundation Series
Platform: Windows NT |
2
Weeks |
| 4 |
Analog
Mixed Signal Design |
ELDO
Advance MS
Platform: Sun Platform |
2
Weeks |
| 5 |
Digital
ASIC Backend |
IC
Station Calibre
Platform: Sun Platform |
2
Weeks |
| 6 |
DSP
VLSI Design |
ModelSim
for Simulation
Leonardo for Synthesis
Xilinx Foundation Series
Platform: Windows NT |
2
Weeks |
| 7 |
Crash
Course in VLSI Design |
Full
EDA Tool Flow
FPGA Design Methodology
ASIC Design Methodology
Analog Mixed Signal Design |
1
Week |